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integrated circuit systems, inc. ics9fg107 0863c?11/22/04 pin configuration recommended application: frequency timing generator for differential cpu, pci express & sata clocks features: generates common cpu/pci express frequencies from 14.318 mhz or 25 mhz crystal or reference input 7 - 0.7v current-mode differential output pairs 3 - 33mhz pci outputs 1 - refout supports serial-ata at 100 mhz two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread unused inputs may be disabled in either driven or hi-z state for power management. key specifications: output cycle-to-cycle jitter for dif outputs < 50 ps (<85ps @ 266 mhz) output to output skew for dif outputs < 85 ps +/-300 ppm frequency accuracy on output clocks programmable ftg for differential cpu, pci express* & sata clocks 48-pin ssop & tssop xin/clkin 1 48 vdda x2 2 47 gnda vdd 3 46 iref gnd 4 45 *dwnsprd# *fs2/refout 5 44 **fs1 gnd 6 43 *oe_0 *fs0/pciclk_f 7 42 dif_0 pciclk0 8 41 dif_0# pciclk1 9 40 vdd vdd 10 39 dif_1 **oe_6 11 38 dif_1# dif_6 12 37 **oe_1 dif_6# 13 36 vdd vdd 14 35 gnd gnd 15 34 **oe_2 **oe_5 16 33 dif_2 dif_5 17 32 dif_2# dif_5# 18 31 vdd vdd 19 30 dif_3 dif_4 20 29 dif_3# dif_4# 21 28 *oe_3 *oe_4 22 27 **sel14m_25m# sdata 23 26 *spread sclk 24 25 dif_stop# notes: pins preceeded by * have 120 kohm pull down resistors pins preceeded by ** have 120 kohm pull up resistors ics9fg107 frequency select table sel14m_25m# (fs3) fs2fs1fs0output(mhz) 0 000 100.00 0 001 125.00 0 010 133.33 0 011 166.67 0 100 200.00 0 101 266.66 0 110 333.33 0 111 400.00 1 000 100.00 1 001 125.00 1 010 133.33 1 011 166.67 1 100 200.00 1 101 266.66 1 110 333.33 1 111 400.00 *other names and brands may be claimed as the property of others.
2 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 pin description pin # pin name pin type description 1 xin/clkin in crystal input or reference clock input 2 x2 out crystal output, nominally 14.318mhz 3 vdd pwr power supply, nominal 3.3v 4 gnd pwr ground pin. 5 *fs2/refout i/o frequency select latch input pin / reference clock output 6 gnd pwr ground pin. 7 *fs0/pciclk_f i/o frequency select latch input pin / 3.3v pci free running clock output. 8 pciclk0 out pci clock output. 9 pciclk1 out pci clock output. 10 vdd pwr power supply, nominal 3.3v 11 **oe_6 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 12 dif_6 out 0.7v differential true clock outputs 13 dif_6# out 0.7v differential complement clock outputs 14 vdd pwr power supply, nominal 3.3v 15 gnd pwr ground pin. 16 **oe_5 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 17 dif_5 out 0.7v differential true clock outputs 18 dif_5# out 0.7v differential complement clock outputs 19 vdd pwr power supply, nominal 3.3v 20 dif_4 out 0.7v differential true clock outputs 21 dif_4# out 0.7v differential complement clock outputs 22 *oe_4 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 23 sdata i/o data pin for smbus circuitry, 5v tolerant. 24 sclk in clock pin of smbus circuitry, 5v tolerant.
3 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 pin description (continued) pin # pin name pin type description 25 dif_stop# in active low input to stop differential output clocks. 26 *spread in asynchronous, active high input, with internal 120kohm pull-up resistor, to enable spread spectrum functionality. 27 **sel14m_25m# in select 14.31818 mhz or 25 mhz input frequency. 1 = 14.31818 mhz, 0 = 25 mhz 28 *oe_3 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 29 dif_3# out 0.7v differential complement clock outputs 30 dif_3 out 0.7v differential true clock outputs 31 vdd pwr power supply, nominal 3.3v 32 dif_2# out 0.7v differential complement clock outputs 33 dif_2 out 0.7v differential true clock outputs 34 **oe_2 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 35 gnd pwr ground pin. 36 vdd pwr power supply, nominal 3.3v 37 **oe_1 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 38 dif_1# out 0.7v differential complement clock outputs 39 dif_1 out 0.7v differential true clock outputs 40 vdd pwr power supply, nominal 3.3v 41 dif_0# out 0.7v differential complement clock outputs 42 dif_0 out 0.7v differential true clock outputs 43 *oe_0 in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 44 **fs1 i/o frequency select latch input pin / 3.3v 66.66mhz clock output. 45 *dwnsprd# in 3.3v input that selects spread mode. this input is not latched at power up. 0 = down spread, 1 = center spread 46 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 gnda pwr ground pin for the pll core. 48 vdda pwr 3.3v power for the pll core. pins preceeded by * have 120 kohm pull down resistors pins preceeded by ** have 120 kohm pull up resistors
4 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 ics9fg107 is a frequency timing generator that provides 7 differential output pairs that are compliant to the intel ck409/ ck410 specification. it provides support for pci-express, next generation i/o, and sata. the part synthesizes several output frequencies from either a 14.31818 mhz crystal or a 25 mhz crystal. the device can also be driven by a reference input clock instead of a crystal. it provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps. ics9fg107 also provides a copy of the reference clock and 3 33 mhz pci output clo cks. f requency selection can be accomplished via strap pins or smbus control. general description block diagram power groups i ref programmable spread pll1 programmable frequency dividers x2 xin/clkin sdata sclk refout dif_stop# sel14m_25m# spread dwnsprd# oe (6:0) fs (2:0) control logic dif (6:0) dif# (6:0) pciclk (1:0) pciclk_f vdd gnd 34 10 6 14,19,31,36,40 15,35 n/a 47 48 47 iref analo g vdd & gnd for pll core descri p tion pin number refout, di g ital inputs, smbus dif outputs pci outputs
5 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 absolute max symbol parameter min max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ua i il1 v in = 0 v; inputs with no pull- up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua full active, c l = full load; f = 400 mhz 250 ma full active, c l = full load; f = 100 mhz 200 ma input frequency 3 f i v dd = 3.3 v 14 25 mhz 3 pin inductance 1 l p in 7nh1 c in logic inputs 1.5 5 pf 1 c ou t output pin capacitance 6 pf 1 clk stabilization 1,2 t stab from v dd power-up and after input clock stabilization to 1st clock 1.8 ms 1,2 modulation frequency f mod triangular modulation 30 40 khz 1 dif output enable t difoe dif output enable after dif_stop# de-assertion 10 ns 1 input rise and fall times t r /t f 20% to 80% of vdd 5 ns 1 1 guaranteed by design and characterization, not 100% tested in production. 2 see timing diagrams for timing requirements. 3 input frequency should be measured at the refout pin and tuned to ideal 14.31818mhz or 25 mhz to meet ppm frequency accuracy on pll outputs. input/output capacitance 1 input low current i dd3. 3op operating supply current
6 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 electrical characteristics - dif 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 , r p =49.9 ! ! ref ! ! 9, parameter symbol conditions min typ max units notes current source output impedance zo 1 v o = v x 3000 1 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g e vovs 1150 1 min volta g evuds -300 1 crossin g volta g e (abs) vcross(abs) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossing over all ed g es 140 mv 1 lon g accuracy ppm see tperiod min-max values -300 300 ppm 1,2 400mhz nominal 2.4993 2.5008 ns 2 400mhz spread 2.4993 2.5133 ns 2,3 333.33mhz nominal 2.9991 3.0009 ns 2 333.33mhz spread 2.9991 3.016 ns 2,3 266.66mhz nominal 3.7489 3.7511 ns 2 266.66mhz spread 3.7489 3.77 ns 2,3 200mhz nominal 4.9985 5.0015 ns 2 200mhz spread 4.9985 5.0266 ns 2,3 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz spread 5.9982 6.0320 ns 2,3 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz spread 7.4978 5.4000 ns 2,3 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz spread 9.9970 10.0533 ns 2,3 400mhz nominal/spread 2.4143 ns 1,2 333.33mhz nominal/spread 2.9141 ns 1,2 266.66mhz nominal/spread 3.6639 ns 1,2 200mhz nominal/spread 4.8735 ns 1,2 166.66mhz nominal/spread 5.8732 ns 1,2 133.33mhz nominal/spread 7.3728 ns 1,2 100.00mhz nominal/spread 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 85 ps 1 measurement from differential wavefrom f not equal 266 mhz 50 ps 1 measurement from differential wavefrom f = 266 mhz 85 ps 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 3 fi g ures are for down spread. statistical measurement on single ended signal using oscilloscope math function. jitter, cycle to cycle t jcyc-cyc 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz or 25 mhz mv measurement on single ended si g nal usin g absolute value. mv t absmin average period tperiod absolute min period
7 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 electrical characteristics - pciclk/pciclk_f t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 33.33mhz output nominal 29.99100 30.00900 ns 2 33.33mhz output spread 29.99100 30.15980 ns 2 33.33mhz output nominal 29.49100 30.50900 ns 2 33.33mhz output spread 29.49100 30.65980 ns 2 clk high time t h1 12 n/a ns 1 clock low time t l1 12 n/a ns 1 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 edge rate falling edge rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.4 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.4 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 250 ps 1 1 guaranteed by design, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz or 25 mhz clock period t period output high current i oh output low current i ol absolute min/max clock period t abs electrical characteristics - ref-14.318/25 mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbo l conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 0 300 ppm 1 14.318mhz output nominal 69.8270 69.8413 69.8550 ns 1,2 25.000mhz output nominal 39.9880 40.0000 40.0120 ns 1,2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.6 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.6 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 160 250 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818 or 25.00 mhz clock period t period
8 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 general smbus serial interface information for the ics9fg107 how to write: ? controller (host) sends a start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address dd (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack
9 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 i 2 c table: device control register, read/write address (dc/dd) pin # name control function type 0 1 pwd bit 7 r w pin 27 bit 6 rw pin 5 bit 5 r w pin 44 bit 4 r w pin 7 bit 3 rw off on pin 26 bit 2 rw hardware select software select 0 bit 1 rw driven hi-z 0 bit 0 rw down center pin 45 notes: 1. these bits reflect the latched state of the corresponding pins at power up, but may be written to if byte 0, bit 2 is set to '1'. fs3 is the sel14m_25m# pin. i 2 c table: output enable register pin # name control function type 0 1 pwd bit 7 pciclk0 output enable rw stop low enable 1 bit 6 dif_6 output enable rw disable enable 1 bit 5 dif_5 output enable r w disable enable 1 bit 4 dif_4 output enable r w disable enable 1 bit 3 dif_3 output enable r w disable enable 1 bit 2 dif_2 output enable r w disable enable 1 bit 1 dif_1 output enable rw disable enable 1 bit 0 dif_0 output enable rw disable enable 1 i 2 c table: output stop mode register pin # name control function type 0 1 pwd bit 7 pciclk1 output enable rw stop low enable 1 bit 6 dif_6 stop mode rw free-run stop-able 0 bit 5 dif_5 stop mode rw free-run stop-able 0 bit 4 dif_4 stop mode rw free-run stop-able 0 bit 3 dif_3 stop mode rw free-run stop-able 0 bit 2 dif_2 stop mode rw free-run stop-able 0 bit 1 dif_1 stop mode r w free-run stop-able 0 bit 0 dif_0 stop mode rw free-run stop-able 0 44 7 byte 0 27 5 26 spread enable 1 - enable software control of frequency, spread enable and spread type dif_stop# drive mode 45 dwnsprd# 1 byte 1 8 12,13 17,18 20,21 30,29 33,32 39,38 42,41 byte 2 9 12,13 17,18 20,21 30,29 33,32 see frequency selection table, page 1 fs3 1 fs2 1 fs1 1 fs0 1 39,38 42,41
10 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 i 2 c table: frequency select readback register pin # name control function type 0 1 pwd bit 7 sel14m_25m# 1 (fs3) state of pin 27 r pin 27 bit 6 fs2 1 state of pin 6 r pin 5 bit 5 fs1 1 state of pin 44 r pin 44 bit 4 fs0 1 state of pin 7 r pin 7 bit 3 spread 1 state of pin 26 r off on pin 26 bit 2 rx bit 1 rx bit 0 dwnsprd 1 state of pin 45 r down center pin 45 notes: 1. these read-only bits always reflect the latched state of the corresponding pins at power up. i 2 c table: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 i 2 c table: device id pin # name control function type 0 1 pwd bit 7 r0 bit 6 r0 bit 5 r0 bit 4 r0 bit 3 r0 bit 2 r1 bit 1 r1 bit 0 r1 reserved reserved device id = 07 hex bit 7 is msb reserved reserved reserved reserved reserved reserved 5 27 7 44 byte 3 26 reserved reserved reserved reserved 45 byte 4 - revision id - - - - vendor id - - - byte 5 - - - - - - - see frequency selection table, page 1 -
11 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 i 2 c table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 byte 6 - writing to this register will configure how many bytes will be read back, default is 07 = 7 b y tes. - - - - - - -
12 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 asserting dif_stop# pin stops all dif outputs that are set to be stoppable after their next transition. when the i2c dif_stop tri-state bit corresponding to the dif output of interest is programmed to a '0', dif output will stop dif_true = high and dif_complement = low. when the i2c dif_stop tri-state bit corresponding to the dif output of interest is programmed to a '1', difoutputs will be tri-stated. dif_stop# - assertion (transition from '1' to '0') with the de-assertion of dif_stop# all stopped dif outputs will resume without a glitch. the maximum latency from the de-assertion to active outputs is 2 - 6 dif clock periods. if the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped dif outputs will be driven high within 10ns of dif_stop# de-assertion to a voltage greater than 200mv. dif_stop# - de-assertion (transition from '0' to '1') dif_stop# dif dif# dif_stop# tdrive_dif_stop, 10ns >200mv dif dif# dif internal
13 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) ordering information ics9fg107 y flft example: designation for tape and reel packaging lead option (optional) lf = lead free ln = lead free annealed package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y f lx t
14 integrated circuit systems, inc. ics9fg107 0863c?11/22/04 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 reference doc.: jedec publication 95, mo-153 in millimeters in inches common dimensions 0.50 basic 0.020 basic 8.10 basic 0.319 basic n d (inch) see variations see variations d mm. 48-lead, 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol see variations common dimensions see variations ordering information ics9fg107 y glft example: designation for tape and reel packaging lead option (optional) lf = lead free ln = lead free annealed package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device ics xxxx y g lx t
g l o b a l s i t e s a ? a ? a ? a ? a ? a ? a ? g l o b a l s i t e s a ? a ? a ? a ? a ? a ? a ? ? ? ? e m a i l ? | ? p r i n t s e a r c h e n t i r e s i t e s e a r c h e n t i r e s i t e c o n t a c t i d t ? | ? i n v e s t o r s ? | ? p r e s s d o c u m e n t s e a r c h ? | ? p a c k a g e s e a r c h ? | ? p a r a m e t r i c s e a r c h ? | ? c r o s s r e f e r e n c e s e a r c h ? | ? g r e e n & r o h s ? | ? c a l c u l a t o r s ? | ? t h e r m a l d a t a ? | ? r e l i a b i l i t y & q u a l i t y ? | ? m i l i t a r y ? 9 f g 1 0 7 ( p c i e / h c s l f r e q u e n c y g e n e r a t o r s ) d e s c r i p t i o n f r e q u e n c y t i m i n g g e n e r a t o r f o r d i f f e r e n t i a l c p u , p c i e x p r e s s & s a t a c l o c k s m a r k e t g r o u p p c c l o c k a d d i t i o n a l i n f o i c s 9 f g 1 0 7 i s a f r e q u e n c y t i m i n g g e n e r a t o r t h a t p r o v i d e s 7 d i f f e r e n t i a l o u t p u t p a i r s t h a t a r e c o m p l i a n t t o t h e i n t e l c k 4 0 9 / c k 4 1 0 s p e c i f i c a t i o n . i t p r o v i d e s s u p p o r t f o r p c i - e x p r e s s , n e x t g e n e r a t i o n i / o , a n d s a t a . t h e p a r t s y n t h e s i z e s s e v e r a l o u t p u t f r e q u e n c i e s f r o m e i t h e r a 1 4 . 3 1 8 1 8 m h z c r y s t a l o r a 2 5 m h z c r y s t a l . t h e d e v i c e c a n a l s o b e d r i v e n b y a r e f e r e n c e i n p u t c l o c k i n s t e a d o f a c r y s t a l . i t p r o v i d e s o u t p u t s w i t h c y c l e - t o - c y c l e j i t t e r o f l e s s t h a n 8 5 p s a n d o u t p u t - t o - o u t p u t s k e w o f l e s s t h a n 8 5 p s . i c s 9 f g 1 0 7 a l s o p r o v i d e s a c o p y o f t h e r e f e r e n c e c l o c k a n d 3 3 3 m h z p c i o u t p u t c l o c k s . f r e q u e n c y s e l e c t i o n c a n b e a c c o m p l i s h e d v i a s t r a p p i n s o r s m b u s c o n t r o l . ? g e n e r a t e s c o m m o n c p u / p c i e x p r e s s f r e q u e n c i e s f r o m 1 4 . 3 1 8 m h z o r 2 5 m h z ? c r y s t a l o r r e f e r e n c e i n p u t ? 7 - 0 . 7 v c u r r e n t - m o d e d i f f e r e n t i a l o u t p u t p a i r s ? 3 - 3 3 m h z p c i o u t p u t s ? 1 - r e f o u t ? s u p p o r t s s e r i a l - a t a a t 1 0 0 m h z ? t w o s p r e a d s p e c t r u m m o d e s : 0 t o - 0 . 5 d o w n s p r e a d a n d + / - 0 . 2 5 % c e n t e r s p r e a d ? u n u s e d i n p u t s m a y b e d i s a b l e d i n e i t h e r d r i v e n o r h i - z s t a t e f o r p o w e r m a n a g e m e n t . a d d t o m y i d t ? [ ? ] h o m e > p r o d u c t s > t i m i n g s o l u t i o n s > p c - n o t e b o o k - s e r v e r c l o c k s > p c i e / h c s l b u f f e r s a n d g e n e r a t o r s > p c i e / h c s l f r e q u e n c y g e n e r a t o r s > 9 f g 1 0 7 y o u m a y a l s o l i k e . . . r e l a t e d o r d e r a b l e p a r t s
a t t r i b u t e s 9 f g 1 0 7 a g 9 f g 1 0 7 a g l n 9 f g 1 0 7 a g l n t v o l t a g e 3 . 3 v ( p a 4 8 ) ? 3 . 3 v ( p a g 4 8 ) ? 3 . 3 v ( p a g 4 8 ) ? p a c k a g e t s s o p 4 8 ? t s s o p 4 8 ? t s s o p 4 8 ? s p e e d n a ? n a ? n a ? t e m p e r a t u r e c ? c ? c ? s t a t u s a c t i v e ? a c t i v e ? a c t i v e ? s a m p l e y e s ? y e s ? n o ? m i n i m u m o r d e r q u a n t i t y 1 5 2 ? 1 5 2 ? 1 0 0 0 ? f a c t o r y o r d e r i n c r e m e n t 3 8 ? 3 8 ? 1 0 0 0 ? t y p e t i t l e s i z e r e v i s i o n d a t e d a t a s h e e t ? 9 f g 1 0 7 d a t a s h e e t 1 0 8 k b 0 3 / 2 7 / 2 0 0 6 p r o d u c t c h a n g e n o t i c e ? p c n # : t b - 0 5 1 0 - 0 5 n e w s h i p p i n g t u b e f o r t s s o p / t v s o p / t s s o p e x p o s e d 2 0 2 k b 1 2 / 1 3 / 2 0 0 5 r e l a t e d d o c u m e n t s h o m e ? | ? s i t e m a p ? | ? a b o u t i d t ? | ? p r e s s r o o m ? | ? i n v e s t o r r e l a t i o n s ? | ? t r a d e m a r k ? | ? p r i v a c y p o l i c y ? | ? c a r e e r s ? | ? r e g i s t e r ? | ? c o n t a c t u s ? u s e o f t h i s w e b s i t e s i g n i f i e s y o u r a g r e e m e n t t o t h e a c c e p t a b l e u s e a n d p r i v a c y p o l i c y . c o p y r i g h t 1 9 9 7 - 2 0 0 7 i n t e g r a t e d d e v i c e t e c h n o l o g y , i n c . a l l r i g h t s r e s e r v e d . n o d e : w w w . i d t . c o m

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